ASIC/RTL Design Engineer - Onsite

Company: Viva USA Inc.
Location: Santa Clara
Posted on: June 1, 2025

Job Description:

Title: ASIC/RTL Design Engineer - Onsite

Do you have the right skills and experience for this role Read on to find out, and make your application.



















Description:





KEY RESPONSIBILITIES:

Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
Collaborate with architecture and hardware teams to understand the requirements.
Work with verification and physical design teams to achieve high quality design and successful tape out.
Design and implement logic functions that enable efficient test and debug.
Participate in silicon bring-up for features owned.
Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.
Implement automation to increase design team efficiency.

EXPERIENCE:

Required

5-6+ years' experience required
Must have proven track record of ASIC design on several production tape-outs.
Experience in Designing RTL block for an SOC.
Experience in integrating ASIC IP into an SOC.
Experience with synthesis, static timing analysis & optimizations.

Nice-to-have:

Experience writing timing constraints and exceptions.
Experience with automation using scripting techniques such as PERL, Python or Tcl
Experience in Power-saving techniques.
Experience with Arm architecture and APB, AXI, CHI protocols.
Experience with design involving Interconnects.
Ability to develop clear and concise engineering documentation.
Ability to organize and present complex technical information.
Strong verbal and written communication skills

EDUCATION: Bachelor's degree required

Top 3 skills: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have






Mandatory skills:



SystemVerilog, ASIC design, RTL block design, SOC integration, synthesis, static timing analysis,
ASIC, ASIC design,
ASIC IP, SOC, RTL,
PERL, Python, Tcl,
Arm architecture, APB, AXI, CHI,
SystemVerilog, Lint, CDC, STA, Silicon,
Power saving techniques, Interconnects,
micro architecture documentation,
engineering documentation, technical information,
synthesis, static timing analysis, optimization, automation,
architecture, hardware, logic functions, test, debug, quality design, production,
design, develop, organization, communication, analysis, collaboration, problem solving, implementation




VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at hr@viva-it.com for any complaints, comments and suggestions.




Contact Details :




Account co-ordinator: Godwin D Antony Raj, Phone No: (847) 607-1014, Email id: staffing10@viva-it.com



VIVA USA INC.
3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008
staffing10@viva-it.com - http://www.viva-it.com

Keywords: Viva USA Inc., Livermore , ASIC/RTL Design Engineer - Onsite, Engineering , Santa Clara, California